Came across the network to the work of a man involved in a similar case, the truth on a deeper level, in order to create an accurate emulator processor 6502 (pictured right picture of the crystal) which is much simpler than 80286 and the task of detailed analysis of the chip looks more real, the since the author has nearly finished the process:
Theme 1 (ru)
Topic 2 (en)
Most of all struck by the fact that he almost always painted all up to the transistor circuit. But the truth of the selected process technology and chip it rougher on the order, and all the structures are much better distinguished. Some of his experience will be useful to me, because I saw a similar structure and in its chip. For example the following figure shows the functionally similar elements in the chips 6502 and 80286, namely a matrix of elements, performs the conversion of one signal type to another, for example it may be in decoding the command code signals to specific output lines:
Here, in both cases, the initial group of signals supplied via the vertical bus, and the resultant signal appears on one or more horizontal lines. If 80286 is even possible to see the characteristic points of the intersections, which encode the logic of transformation, in the case of the 6502 chip encoding is hidden in the deeper layer, which is not seen in this photo.
The 80286 processor, such matrices are scattered throughout the crystal, performing management functions in the field. Some of them even at the entrance to have something that can be counter and thus the decoder itself complete with a binary counter can provide multi-step control sequences encoding performance of some multi-cycle instructions.
The following function block, the purpose of which was able to understand, is a 6-byte instruction prefetch queue processor. Moreover, in different sources, this represents that all 6-byte is 8-byte. The following picture shows that the queue is organized into three registers (three red rectangle), where data is loaded from the 16-bit bus, and is read byte by byte via the upper line. And which half of the register to be read is controlled by the orange line (H/L) and what it would take or register data is determined to give the green control lines:
On the basis of this scheme we can say that there is no pre-decoding stored in the queue are not the team, and it’s really just a prefetch buffer, allowing the team to read from RAM 16-bit words at a few steps forward. And what’s interesting – the registers do not really 16-bit and 18-bit! That is added to each byte some service information bit (purple line in the diagram). Perhaps it points to a senior or junior byte is 16-bit word.