In a previous article (Part 1) I started studying what the 80286 microprocessor in terms of circuitry. In this article, I will continue to deepen in its micro-architecture, considering the picture of the crystal and to speculate on the basis of their knowledge. At the same time, I note that all managed to understand on a separate layer in Photoshop, and is ready to share with all the desired results.
For a better understanding we try to understand what we see of the structure surrounding the contact pads of the chip. First, a little theory – see the diagram looks like a simplified diagram of the output element of the chip. Depending on the level of the signal Vin. submitted simultaneously to the gates of the two transistors one of them closed, and in the second on Vout. gets potential VCC or VSS, respectively, which represents a 1 or a 0. Why do we need these transistors when the output logic and so all signals are 0 and 1? Then, these signals are so weak that for them, even the track on the circuit board is already a burden, not to mention the fact, to connect one or more inputs of logic circuits.
The following photos are not difficult to notice that the output transistors (VT1, VT2) have huge dimensions, compared to those who used to organize the logic inside the chip. True, unlike the scheme above, here we see that the valves VT1 and VT2 are controlled by separate voltages – U1, U2. This is because that the PIN may be the third state – Z, passing in which he becomes capable of receiving the input signal (IN) whose direction is indicated by a green arrow.
What’s interesting – the input CLK signal without any internal buffers and approvals, just like that as it is – with pad walked around the perimeter of the crystal. In the course following the branching towards the areas S0, S1, BHE, LOCK, M / IO, COD / INTA, where the clock signal for gating out probably output signals. With the same purpose, he served in the buffer elements of the data bus D0-D15. Closing the circle, he returns to the site CLK. I did not notice I only branches to the address bus platforms, but further I saw that these signals are gated been the main generator clock, as detailed below.
To synchronize the internal units of the crystal CLK signal goes through some circuit comprising a still huge mnogokollektornye and mnogoemitternye transistors. It looks at all the largest in the entire crystal transistors, because they synchronize all blocks and microcontroller must withstand very high load in the form of thousands of items. Judging by the photos of this signal generator – a huge transistor 4, divided into two pairs, and go in different directions on a pair of wide conductors, venture to suggest that one of them repeats the clock pulses CLK and the second does the same in the opposite.
I outlined these signals CLK-U and CLK-D – for the upper and lower block, respectively. In the picture arrows indicate the direction in which these signals are mutually divergent. The total area of these blocks is about 1% of the crystal!
The datasheet indicated that inside the CLK is divided by 2, then CLK-U and CLK-D likely operate at half the frequency.